1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a circuit structure of a shift register.
2. Description of the Prior Art
Generally, a display panel includes a plurality of pixels, a gate driver, and a source driver. The gate driver includes a plurality of stages of shift registers and is used to provide a plurality of gate driving signals for turning on and off the pixels. The source driver is used to write the data into the turned-on pixels.
FIG. 1 shows the shift register circuit 100 according to prior art. The shift register circuit 100 includes switches T1A, T1B, T1E, T1G, T1H, T1K, T1L, T1M and T1N. The switch T1A has a first terminal for receiving a clock signal CK, a second terminal as an output terminal ON of the shift register circuit 100 for outputting a scan signal GN of the shift register 100, and a control terminal electrically coupled to a node QN of the shift register circuit 100. The switch T1B has a first terminal for receiving a scan signal GN−1 outputted from an N−1 stage of shift register circuit, a second terminal electrically coupled to the node QN, and a control terminal electrically coupled to the first terminal of the switch T1B. The switch T1E has a first terminal electrically coupled to the node QN, the second terminal electrically coupled to a system voltage terminal Vss, and a control terminal for receiving a scan signal GN+2 outputted from an N+2 stage of shift register circuit. The switch T1G has a first terminal for receiving a high voltage level VGH, and a control terminal electrically coupled to the first terminal of the switch T1G. The switch T1H has a first terminal electrically coupled to the first terminal of the switch T1G, and a control terminal electrically coupled to a second terminal of the switch T1G. The switch T1K has a first terminal electrically coupled to a second terminal of the switch T1G, a second terminal electrically coupled to the system voltage terminal Vss, and a control terminal electrically coupled to the node QN. The switch T1L has a first terminal electrically coupled to the second terminal of the switch T1H, a second terminal electrically coupled to the system voltage terminal Vss, and a control terminal electrically coupled to the node QN. The switch T1M has a first terminal electrically coupled to the node QN, a second terminal electrically coupled to the second terminal of the switch T1A, and a control terminal electrically coupled to the second terminal of the switch T1H. The switch T1N has a first terminal electrically coupled to the second terminal ON of the switch T1A, a second terminal electrically coupled to the system voltage terminal Vss, and a control terminal electrically coupled to the second terminal of the switch T1H. The system voltage terminal Vss can used to provide a low voltage level VGL.
FIG. 2 is the timing diagram of the shift register 100. During the period T1, the scan signal GN−1 is pulled up to the high voltage level VGH, the scan signal GN+2 remains at the low voltage level VGL, and the clock signal CK is at the low voltage level VGL. At this time, the switch T1B is turned on so the voltage level of the node QN is also pulled up to the high voltage level VGH, which turns on the switch T1A and controls the voltage level of the scan signal GN to remain at the same low gate voltage level VGL as the clock signal CK. The switches T1G, T1K and T1L are turned on. However, since the driving power of the switch T1K is stronger than the driving power of the switch T1G, the control terminal of the switch T1H is kept at the low voltage level VGL and is turned off and the voltage level of the second terminal of the switch T1H is also kept at the low voltage level VGL turning off the switches T1M and T1N. The switch T1E is also turned off.
During the period T2, the scan signal GN−1 is changed back to the low voltage level VGL, the scan signal GN+2 is kept at the low voltage level VGL, and the clock signal CK is changed to the high voltage level VGH. At this time, the switch T1B is turned off and the switch T1A is still turned on, which pulls up the voltage level of the scan signal GN to the high voltage level VGH as the clock signal CK. The voltage level of the node QN is pulled up to a voltage level that is about two times the high voltage level VGH (that is, 2VGH) due to the coupling effect of the capacitor C1. The switches T1G, T1K, T1L are still turned on and the switches T1H, T1M, T1N and T1E are still turned off. In addition, during the period of T2, although the high voltage level of the node QN can pull up the voltage level of the scan signal GN to the high voltage level VGH quickly, it also enlarges the source-drain voltage gap Vds of the switch T1B and the source-drain voltage gap Vds of the switch T1E, which are close to two times high voltage level 2VGH. Such high source-drain voltage gap Vds can usually cause big current leakage, pull down the voltage level of the QN and weaken the driving power of the switch T1A to pull up the scan signal GN.
During the period T3, the scan signals GN−1 and GN+2 are both kept at the low voltage level VGL, and the clock signal CK is changed to the low voltage level VGL. The switch T1B is still turned off and the switch T1A is kept turned on so the scan signal GN is pulled down to the same low voltage level VGL as the clock signal CK. The switches T1G, T1K and T1L are still turned on and the switches T1H, T1M, T1N and T1E are still turned off.
During the period of T4, the scan signal GN−1 is kept at the low voltage level VGL, the scan signal GN+2 is changed to the high voltage level VGH, and the clock signal CK is still at the low voltage level VGL. The switch T1B is still turned off and the switch T1E is turned on so the voltage level of the node QN is pulled down to the low voltage level VGL. Thus, the switches T1A, T1K, and T1L are tuned off. The switch T1G is kept turned, which also turns on the switches T1H, T1M and T1N so the voltage levels of the node QN and the scan signal GN are both kept at the low voltage level VGL stably.
As the resolution of the display panel becomes higher and higher, the time for the source driver to transmit a bit of pixel information is also shortened. However, since the driving power of the switch T1A to pull up the scan signal GN is weakened due to the current leakage on the switches T1B and T1E as the operations of the shift register circuit 100 in the period T2 shown in FIG. 2, the transition of the voltage level of the scan signal GN may not be fast enough and may cause wrong charging of the pixels of the display panel.